A. Field of the Invention
This invention relates to electronic circuits, and more particularly to digital to analog converters having alternate binary and binary code decimal (BCD) modes of operation.
B. Description of the Prior Art
BCD is a logic coding format having less stringent linearity requirements for digital to analog converters than binary coding. Depending upon the requirements of the particular application, a digital to analog converter (DAC) may be constructed to operate in either a binary or a BCD mode. The two coding systems are illustrated in FIG. 1. With binary coding each digit or bit has double the value of the preceding bit. The binary coding for the no. 729, occupying 10 bits, is shown as an example. BCD coding, on the other hand, is a combination of the binary and decimal systems. The code is arranged in groups of four bits, or quads, with the four bits in each successive quad providing a binary code representation of successively higher order decimal numbers. For example, the first four bits (reading from left to right) represent the numbers 0 through 9 multiplied by 100, the second four bits represent 0 through 9 multiplied by 10, and the third four bits represent 0 through 9. Thus, 12 bits grouped into three quads are necessary to form the numbers 0 through 999, with the BCD code for the number 729 given for purposes of illustration. Since the largest decimal number for any one quad is a decimal multiple of 9, maximum or full-scale output is attained when the first and fourth bits of the quad are on; it is not permissible to have all of the bits on at the same time for BCD.
Prior art DAC's capable of BCD operation generally follow the design pattern shown in FIG. 2, with three essentially independent DAC's 2, 4 and 6 (shown enclosed in dashed lines). Each quad consists of four bit circuits for a total of 12 bits numbered 1 through 12 for the three decimal number device shown in FIG. 2. Quads 2, 4 and 6 produce output currents representing the numbers 0 through 9 multiplied by a factor of 100 for quad 2, a factor of 10 for quad 4, and a factor of 1 for quad 6. Since the input currents for corresponding bits of the various quads are equal, proper BCD scaling between quads is achieved by using high input currents for each quad and then attenuating the outputs of quads 4 and 6. For this purpose current dividers 8 and 10 are connected between the output lines for quads 2 and 4, and quads 4 and 6 respectively. Output current is drawn from an output terminal 12 into each of the bits, the output for quad 4 being attenuated by a factor of 10 and the output of quad 6 by a factor of 100. With this design most of the current drawn by quads 4 and 6 is wasted, with relatively little of the current appearing at the output. This situation is summarized in FIG. 3, which gives the input current drawn by each bit (in microamperes) and the ultimate output current resulting from each bit. With the first and fourth bits of each quad operating to produce a full-scale output current of 999 microamperes, a total of 2700 microamperes are actually drawn through the individual bits. The difference between these two current levels represents a substantial loss of power in the conversion from binary to BCD operation.
In addition to the power loss, the prior art approach described above involves some further disadvantages. Forcing the bit circuits to be grouped into quads involves a loss of design flexibility, while the use of resistance current dividers to attenuate the output current between quads can produce errors in the relative current weighting assigned to each of the quads. Also, the output terminal must be held at virtual ground to maintain precision attenuation between quads and thus exhibits poor compliance, i.e., an ability to operate over a significant voltage range while maintaining accuracy.
Another problem involves the output voltage level. DAC's are typically employed in a circuit as shown in FIG. 4, with the output of the DAC 14 connected to the positive input of an external operational amplifier 16 for a current to voltage conversion which produces an output voltage signal at output terminal 18. The conversion ratio is controlled by a span resistor 20 connected between the output and positive input of amplifier 16. In the past this configuration has led to a problem in converting from binary to BCD operation due to an industry convention calling for a fixed full-scale voltage (usually 10 volts) at terminal 18, regardless of the DAC mode. Since the binary mode full-scale current output is greater than the BCD full-scale current output by a factor of 1.6, the output voltage at terminal 18 is greater for binary operation than for BCD unless some compensating adjustment is made to the system. In the prior art this adjustment is made by changing the resistance value of span resistor 20 when the full-scale current output is changed. It is desirable and economically efficient for this adjustment to be made at final test after the DAC has been completely manufactured so that devices meeting the stringent linearity requirements can be assigned to binary usage, with the remainder going to BCD. However, since span resistor 20 is generally formed directly on the chip for integrated circuits, it cannot be adjusted to a BCD value at final test with the same precision that it could have originally been built to. As a result this method of binary to BCD conversion introduces the possibility of undesirable errors in the magnitude of the output voltage signal.